1. What are the different layers in MOS transistor?
2. What are the different operating regions for an MOS transistor?
3. What is Enhancement mode transistor?
4. What is Depletion mode device?
5. When the channel is said to be pinched off?
6. What are the steps involved in manufacturing of IC?
7. What is meant by Epitaxy?
8. What are the processes involved in photo lithography?
9. What is the purpose of masking in fabrication of IC?
10. What lire the materials used for masking?
11. What are the types of Photo etching?
12. What is diffusion process? What are doping impurities?
13. What is Ion-Implantation process?
14. What are the various Silicon wafer Preparation?
15. What are the different types of oxidation?
16. What is Isolation?
17. Give the different types of CMOS process?
18. What is Channel-stop Implantation?
19. What is LOCOS?
20. What is SWAMI?
21. What is LDD?
22. What is Twin-tub process? Why it is called so?
23. What are the steps involved in twin-tub process?
24. What are the special features of Twin-tub process?
25. What are the advantages of Twin-tub process?
26. What is SOI? What is the material used as Insulator?
27. What are the advantages and disadvantages of SOI process?
28. What are the advantages of CMOS process?
29. What is the various etching processes used in SOI process?
30. What is BiCMOS Technology?
31. What are the basic processing steps involved in BiCMOS process?
32. What is meant by interconnect? What are the types are of interconnect?
33. What is Silicide?
34. What is Polycide?
35. What is Stick diagram?
36. What are the uses of Stick diagram?
37. Give the various color coding used in stick diagram?
38. Define Threshold voltage in CMOS?
39.What is the difference between Testing & Verification?
40. How do you size NMOS and PMOS transistors to increase the threshold voltage? 41.which language is better as compare to verilog and VHDL and why?
43.what are the universal gates? And why?
44. which gate is related to comparator output?
45.what is the meaning of Leaf Level design? which transistors are used?
46. what is VHDL?
47.what is back annotation method?
48. In FPGA for logic implementation which one we are using?
49.What is LUT?
50. What is CPLD?
VLSI KEY
1. The layers are Substrate, diffused Drain & Source, Insulator (SiO2) & Gate.
2. Cutoff Region
Non- Saturated (Linear) Region
Saturated Region
3. The device that is normally cut-off with zero gate bias is called Enhancement Mode transistor.
4. The Device that conducts with zero gate bias is called Depletion mode device.
5. If a large Vds is applied, this voltage will deplete the inversion layer. This Voltage
Effectively pinches off the channel near the drain.
6. Silicon wafer Preparation
Epitaxial Growth
Oxidation
Photo-lithography
Diffusion
Ion Implantation
Isolation technique
Metallization
Assembly processing & Packaging
7. Epitaxy means arranging atoms in single crystal fashion upon a single crystal
Substrate.
8. (1) Masking process
(2) Photo etching process.
These are important processes involved in photolithography.
9. Masking is used to identify the location in which Ion-Implantation should not take
Place.
10. Photo resist, Si02, SiN, Poly Silicon.
11. Wet etching and dry etching are the types of photo etching.
12. Diffusion is a process in which impurities are diffused into the Silicon chip at 1000˚C temperature. B203 and P205 are used as impurities used.
13. It is process in which the Si material is doped with an impurity by making the
Accelerated impurity atoms to strike the Si layer at high temperature.
14. Crystal growth & doping
Ingot trimming & grinding
Ingot slicing
Wafer polishing & etching
Wafer cleaning.
15. The two types of oxidation are Dry & Wet Oxidation.
16. It is a process used to provide electrical isolation between different components
and interconnections.
17. p-well process
n-well process
twin-tub process
SOI process
18. In n-well fabrication, n-well is protected with the resist material. (Because, it should not be affected during Boron implantation). Then Boron is implanted except n-well. The above said process is done using photo resist mask. This type of implantation is known as Channel-stop implantation.
19. LOCOS mean Local Oxidation of Silicon. This is one type of oxide construction.
20. SWAMI means Side Wall Masked Isolation. It is used to reduce bird's beak effect.
21. LDD means Lightly Doped Drain Structures.
It is used for implantation of n- region in n-well process.
22. Twin-tub process is one of the CMOS technologies. Two wells (the other name for well is Tub) are created in this process. So, because of these two tubs, this process is known as Twin-tub process.
23. Tub Formation
Thin-oxide Construction
Source & Drain Implantation
Contact cut definition
Metallization.
24. In Twin-tub process, Threshold voltage, body effects of n and p devices are
Independently optimized.
25. Advantages of Twin-tub process are (1) Separate optimized wells are available.(2) Balanced performance is obtained for n and p transistors.
26. SOI means Silicon-on-Insulator.
In this process, a Silicon based transistor is built on an insulating material like
Sapphire or SiO2.
27. Advantages of SOI process: 1. there is no well formation in this process.2. There is no field-Inversion problem.3. There is no body effect problem.
Disadvantages of SOI process: 1. it is very difficult to protect inputs in this process.2. Device gain is low.3. The coupling capacitance between wires always exists.
28. Low Input Impedance
Low delay Sensitivity to load.
29. Various etching processes used in SOI are,
(A. FULLY ANISTROPHIC ETCHING)
(B. PREFERENTIAL ETCHING)
(C. ISOTROPHIC ETCHING)
30. It is the combination of Bipolar technology & CMOS technology.
31. Additional masks defining P base region
N Collector area
Buried Sub collector (SCCD)
Processing steps in CMOS process
32. Interconnect means connection between various components in an IC.
Types of Inter connect: 1. Metal Inter connect 2. PolySilicon Inter connect 3. Local Inter connect.
33. The combination of Silicon and tantaleum is known as Silicide.
It is used as gate material in Polysilicon Interconnect.
34. The combination of Silicide and Polysilicon is known as Polycide.
It is used as gate material.
35. The diagram which conveys the layer information through the use of various
colours is known as Stick diagram. It is also the cartoon of a chip layout.
36. It can be drawn much easier and faster than a complex layout.
These are especially important tools for layout built from large cells.
37. Green -n- dif f us ion
Red- polysilicon
Blue -m et al
Yellow -implant
Black - contact areas.
38. The Threshold voltage, VT for a MOS transistor can be defined as the voltage applied between the gate and the source of the MOS transistor below which the drain to source current, IDS effectively drops to zero.
39. Testing is checking input and output and verification means verify its response with given data.
40. by increasing channel length of nmos and pmos
41. VHDL
42. when a suitable polarity potential is applied at gate a conducting channel will form. This conducting channel can be used for switching or amplification
43. Nand and Nor
44. Exor
45. Nmos,cmos,pmos
46. VHSIC hardware scripting language.
47. Upto Meet the desired clock we will redesing the process again again that is called back annotation method.
48.LUT
49. Look up table.
50. Complex programable logic devic
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